BOTHEDGE=0, MAEN1=0, TDMAE=0, MAEN2=0, RESYNCDIS=0, RXEDGIE=0, SBNS=0, LBKDIE=0, RDMAE=0, MATCFG=00, M10=0
LPUART Baud Rate Register
| SBR | Baud Rate Modulo Divisor. |
| SBNS | Stop Bit Number Select 0 (0): One stop bit. 1 (1): Two stop bits. |
| RXEDGIE | RX Input Active Edge Interrupt Enable 0 (0): Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). 1 (1): Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. |
| LBKDIE | LIN Break Detect Interrupt Enable 0 (0): Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). 1 (1): Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. |
| RESYNCDIS | Resynchronization Disable 0 (0): Resynchronization during received data word is supported 1 (1): Resynchronization during received data word is disabled |
| BOTHEDGE | Both Edge Sampling 0 (0): Receiver samples input data using the rising edge of the baud rate clock. 1 (1): Receiver samples input data using the rising and falling edge of the baud rate clock. |
| MATCFG | Match Configuration 0 (00): Address Match Wakeup 1 (01): Idle Match Wakeup 2 (10): Match On and Match Off 3 (11): Enables RWU on Data Match and Match On/Off for transmitter CTS input |
| RDMAE | Receiver Full DMA Enable 0 (0): DMA request disabled. 1 (1): DMA request enabled. |
| TDMAE | Transmitter DMA Enable 0 (0): DMA request disabled. 1 (1): DMA request enabled. |
| OSR | Over Sampling Ratio |
| M10 | 10-bit Mode select 0 (0): Receiver and transmitter use 8-bit or 9-bit data characters. 1 (1): Receiver and transmitter use 10-bit data characters. |
| MAEN2 | Match Address Mode Enable 2 0 (0): Normal operation. 1 (1): Enables automatic address matching or data matching mode for MATCH[MA2]. |
| MAEN1 | Match Address Mode Enable 1 0 (0): Normal operation. 1 (1): Enables automatic address matching or data matching mode for MATCH[MA1]. |